1. Field of the Invention
The present invention relates to a semiconductor memory device, an operational device and a memory system, and particularly to a memory device and memory system that can implement a processing system capable of fast operation. More particularly, the invention relates to a memory device, a processing system and a memory system using a Magnetic Random Access Memory (MRAM) in which an element such as a TMR (Tunneling MagnetoResistance) element or a MTJ (Magnetic Tunneling Junction) element utilizing a magnetoresistance effect, are employed for a memory element.
2. Description of the Background Art
In a processing system using a processor such as a microprocessor or a microcontroller, a ROM (Read Only Memory) and a RAM (Random Access Memory) are employed as external memory devices. The ROM is used for storing fixed information such as control data and processing/control programs. The RAM is used as a working area of the processor or the like, and is used for temporarily storing an application program and application data as well as processed data and preprocessed data.
By storing the fixed information in ROM, basic software that may impede a normal operation of the system if destroyed, such as a boot program for starting up a system, BIOS (Basic I/O System) that controls coupling between OS (operating system) as well as an application program and peripheral devices, and basic control data such as identification information are stored.
For the RAM, the storage capacity is set according to an application of processing, for storing a relatively large quantity of information. By utilizing accessibility of the RAM that is faster than that of a disk unit and others, fast data transfer is performed.
For the ROM and RAM, memories of different types may be used. For example, when a mask ROM or a nonvolatile semiconductor memory device (flash memory) that can allow electrical programming and flash erasure is used for the ROM, if storage capacities of such memories is optimized, depending on individual purposes, in system designing, it is required to design memory device systems for each different processing application, resulting in an increased cost in the design, development, production and distribution.
For overcoming the problem of the above system architecture, FeRAM (Ferromagnetic RAM) or a magnetic semiconductor memory (MRAM Magnetic Random Access Memory) can be used as an external memory device, as disclosed in Reference 1 (Japanese Patent Laying-Open No. 2003-104137) and Reference 2 (Japanese Patent Laying-Open No. 2002-025246).
In the construction disclosed in Reference 1, a plurality of MRAM chips are arranged in parallel, storage regions of these MRAM chips are divided into a RAM region and a ROM region, and writing to the ROM region is inhibited.
Reference 1 uses the MRAM for the ROM or RAM, to set the storage capacities (address spaces) of the RAM and ROM regions flexibly according to the application, and intends to simplify a memory architecture and a memory control circuit to reduce a cost and a assembling space.
According to the construction disclosed in Reference 2, the multi-bank FeRAM or MRAM is used, and each bank is allocated to the ROM or RAM region. A write inhibit bit is set in the bank used as the ROM region for inhibiting the write access to this bank.
Reference 2 likewise intends to achieve a simple memory system allowing fast access by using the FeRAM or MRAM for the ROM and RAM.
In the constructions disclosed in References 1 and 2, FeRAM or MRAM is used for ROM or RAM. As compared with the flash memory, FeRAM and MRAM have such features that writing requires a short time, a data holding time is long and the number of rewriting is greatly large.
In References 1 and 2, however, data and program instructions are externally transferred with an outside of the memory device via a common data bus. Thus, information (“information” is used for referring to both data and a program instruction) stored in the ROM and RAM regions is transferred via the common bus or via a common input/output circuit.
Accordingly, an operational processing unit accessing this memory device cannot access in parallel the ROM and RAM regions, and instruction fetch cannot be performed in the same cycle as processing data transfer. This instruction fetch can be performed only after completion of the data access, so that a wait cycle occurs in an external operational processing unit, and an instruction execution speed lowers.
References 1 and 2 intend to simplify the construction of the memory system by replacing the ROM and RAM different in types and operation speeds with FeRAM or MRAM of one type, but no consideration is given to a construction for reducing a wait cycle of the external operational processing unit to improve processing efficiency of an entire processing system.